1.1.1 (d) Flashcards
OCR H446 Computer Science Specification
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give me an overview of pipelining (2 things)
- it's a CPU design technique that improves the instruction throughput - by overlapping the FDE cycles which allows for multiple instructions to be executed simultaneously
what's a misconception of pipelining? (3 things)
- it doesn't execute a single instruction faster - but it allows multiple instructions to be executed continuously simultaneously - therefore, increasing efficiency
what's the specific definition of pipelining? (4 things)
- it's the overlapping of different stages of the instruction cycle - so while one instruction is being fetched - the next instruction is being decoded - and another is being executed
what's the goal of pipelining? (1 thing)
- to maximize CPU utilization + decrease idle time of components
how does pipelining improve efficiency by overlapping FDE cycles? (2 things)
- it allows the idle time of CPU components to decrease - so that all CPU components are working at once
how does pipelining improve efficiency by increasing instruction throughput? (1 thing)
- because it allows for more instructions to be executed per second
how does pipelining improve efficiency by allowing hardware to be used efficiently? (1 thing)
- because it gets the ALU, CU, buses to work at once
how does pipelining improve efficiency by decreasing average execution time per instruction? (1 thing)
- because after the pipeline fills, there's a new result for every clock cycle
what's a data hazard (1 thing)
- when the next instruction needs the result of the previous one that's still in the pipeline
what are the solutions for data hazard (3 things)
- data forwarding - pipeline stalls - execution reordering
what's a control hazard? (1 thing)
- when the next instruction depends on a jump/branch outcome
what are the solutions for the control hazard? (2 things)
- branch prediction - pipeline flush
what's a structural hazard? ( 1 thing)
- when the hardware resources clash
what are the solutions for structural hazards? (2 things)
- duplicate resources - split caches
which instruction length benefit more and why? ( 2 things)
- RISC - because simpler + fixed-length instruction
how does pipelining depend on clock speed? ( 2 things)
- because higher clock speed - because it allows for a faster instruction flow
how does pipelining depend on number of stages? ( 2 things)
- because more stages allows for a higher potential throughput - but there are more risk hazards
how does pipelining depend on branch prediction accuracy? (2 things)
- because a higher accuracy decreases flushes - so it result's in a higher performance
how does out-of-order execution decrease pipeline stalls? ( 1 things)
- the independent instructions are being executed early while waiting for the dependent instructions
how does branch prediction decrease pipeline stalls? ( 1 things)
- by making the CPU guess the outcome of a branch to continue fetching ahead
how does speculative execution decrease pipeline stalls? (2 things)
- by making the CPU execute the predicted path instructions - if the prediction was correct, then it saves time and if not correct, it discards the results
how does data forwarding by passing decrease the pipeline stalls? (1 thing)
- because it passes the result of one stage directly to another without waiting for the register's write-back
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