1.1.1(c) Flashcards

- there are three factors affecting the CPU performance which are clock speed, number of cores, chache memory

- it depends on how quickly the FDE cycle are completed - its measured in instructions per second

- it can have a multicore processor = when multiple FDE cycles are completed in paralell - it has a core which is an independent processing unit that is in the CPU which performs it's own FDE cycle

- each core uses separate threads - a thread is a sequence of instructions - it allows for parallel processing - parallel processing is when instructions are executed simultaneously

- because it increases CPUB throughput - throughput = the number of instructions executed per second - it also allows the CPU to have multitasking - so it can run multiple programs without slowing down

- not all programs can utilize (make effective use of) multicore - because some tasks are single threaded -communication overhead between cores - overhead is when a resource is not used to fulfill a main goal - so it decreases efficiency -parallel programs might experience synchronization delays

- it sends out regular pulses - to synchronize all operations - each pulse is 1 clock cycle - this is done so that one step of the FDE cycle can occur

- it's measured in hertz - e.g. 3.5 GHz = 3.5 billion clock cycles per second

- the higher the clock speed, the more FDE cycles are completed per second - This means that more instructions are processed per second

- yes - so increasing the clock speed, decreases the total execution time

- because it's a key determinant of a single-core performance - and it also determines how fast each instruction can move through the FDE pipeline

- higher clock speed doesn't always double the performance - this is because of bottlenecks e.g. waiting for RAM/ chache misses - higher frequency means higher heat generation and higher power consumption - there are also diminishing returns due to bottlenecks e.g. Memory latency/instruction dependency - there are also physical limits e.g. transistor switching speed

- its a small, ultra fast type if memory that located on/near the CPU chip - it also temporarily stores frequently running data + instructions - so it acts as a buffer between slow main memory (RAM) and fast CPU

- its the fastest and the smallest - it's inside each core - so it stores current instructions/data

- its slower than L1, and larger than L1 - its on the same chip (so it's on every core/shared) - it stores recently used instructions

- it's the slowest an the largest - it decreases memory access delay - so it's built for large datasets

- because it improves the instruction throughput and overall responsiveness - it also increases the memory access speeds, so it's one of the CPU's biggest bottlenecks

- cache memory is expensive - so it limits how much cache is needed - as a result, this causes slow performance

- word size - bus width - instruction set complexity (CISC vs RISC) - pipelining

- = the number of bits the CPU processes in one operation - so the larger the word - the more data is handled per cycle

- the wider the data/address bus - the more data can move/cycle

- the simpler RISC instruction set - allows for faster execution, but it may need more instructions

- it overlaps FDE stages for multiple instructions - so it increases instruction throughput

- it guesses the next instruction - to keep pipeline full + decrease idle cycles