1.1.1 (b) Flashcards

- it repeats millions/billions of times - its the core operational loop of the CPU - it shows how the CPU retrieves, interprets, runs instructions - based on what is stored in main memory

- its a step by step process - that the CPU follows - to carry out one instruction

- by coordinating the CU, registers and buses - so that they can move and process data/instructions

- so that a stored-program computer - can automatically execute instructions - repeatedly and sequentially

- fetch - decode -execute - repeat

- it allows for the instructions to be read from memory - unless a jump/branch changes the PC

- it gets the next instruction to move from main memory into the CPU

1) PC ->MAR - the address of the next instruction gets copied into the PC - then gets copied into the MAR 2) address bus -> memory - the address travels via the address bus - to locate instruction in RAM 3) the control unit sends "memory read" signals via the control bus

4) memory -> MDR - the instruction (binary opcode) is fetched from that memory address - and into the MDR via the data bus 5) MDR -> CIR - the fetched instruction is then copied into the CIR 6) PC is incremented by one, so the next address of the instruction is prepared

- because it converts binary machine code instructions into specific electronic control actions that the hardware can execute

1) The CU examines the opcode in the CIR - because the instruction is split into opcode (what to do) + operand (data/address) 2) The CU decodes the opcode - so it determines which component must act 3) Then the CU generates control signals to activate necessary circuits 4) if the instruction involves operand - the MAR is loaded with that operand's address - so the next fetch will retrieve data

- it carries out decoded instruction

- because it actually performs the task the instruction specifies - so that the flow of the program is updated

1) The CU sends appropriate control signals to execute the instruction 2)Then, the results gets stored back into the ACC/memory 3) Finally, the flag in the status register is updated

- After the execution, the PC already points to the next instruction - then the cycle returns to fetch + repeats until a halt instruction/interrupt occurs

- because a higher clock speed means more FDE cycles are completed per second - because for each FDE stage, it takes one/more clock cycles to to complete one instruction - because it generates regular pulses which coordinates all operations

- because pipelining overlaps FDE cycles - so while one instruction is fetching, the next is decoding and another is executing - but it introduces many hazards e.g. branch misprediction/data dependency

- clock - memory read/memory write - I/O read/write - interrupt request/acknowledge - reset/halt

- clock -> synchronises all operations - memory read/ memory write -> controls the direction of the data transfer when the RAM is being used - I/O read/write -> controls peripheral data flow - interrupt request/acknowledge -> handles priority tasks - reset/halt -> restarts/stops the execution